ENGINEER, DESIGN

Overview

As a Design Engineer in the NVEG group, you own the development of NAND logic features from architecture to RTL and post-silicon validation. You translate system requirements into micro-architecture and robust digital implementations, and drive verification across blocks to full-chip levels. You collaborate with cross-functional teams to optimize performance, power, and reliability, and assist silicon bring-up and debugging to enable robust product ramp. This role sits at the intersection of architecture, firmware, datapath, analog, and test, contributing to new product pathfinding in a world-leading memory company.

Retribuzione / Benefits meal vouchers

corporate welfare

remote working days

supplementary health insurance

life coverage

Employee Assistance Program

Responsabilità Own end-to-end development of logic features from architecture through RTL, verification, and post-silicon validation

Translate system and firmware requirements into micro-architecture specifications and robust digital designs

Develop RTL and drive verification activities (block, subsystem, full-chip) including coverage and post-layout validation

Collaborate with multi-functional teams to define interfaces, ensure integration quality, and optimize performance, power, and reliability

Support silicon bring-up, debug, and root-cause analysis to aid yield learning and product ramp

Requisiti fondamentali M.S. or Ph.D. in Electrical Engineering, Electronics, or related field

Strong experience in digital logic design and verification for complex SoCs or memory products

Hands-on experience with RTL design, gate-level verification, and simulation methodologies

Solid understanding of system-level and micro-architectural design trade-offs (performance, power, reliability)

Strong communication and problem-solving skills, with ability to work effectively in global multi-functional teams

strong communication skills

problem-solving abilities

team collaboration in global multi-functional teams

RTL design

gate-level verification

simulation methodologies